Nested VMX: n2 MSR handling and capability exposure

Signed-off-by: Qing He <qing.he@intel.com>
Signed-off-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Tim Deegan <Tim.Deegan@citrix.com>
Committed-by: Tim Deegan <Tim.Deegan@citrix.com>

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index d59bbd057a02c7bd00efcf0267da48af49f48fec..8374c1dfd5bbcb8cba112e9f1597d3d53f6462d6 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1774,8 +1774,11 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
         *msr_content |= (u64)__vmread(GUEST_IA32_DEBUGCTL_HIGH) << 32;
 #endif
         break;
-    case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
-        goto gp_fault;
+    case IA32_FEATURE_CONTROL_MSR:
+    case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
+        if ( !nvmx_msr_read_intercept(msr, msr_content) )
+            goto gp_fault;
+        break;
     case MSR_IA32_MISC_ENABLE:
         rdmsrl(MSR_IA32_MISC_ENABLE, *msr_content);
         /* Debug Trace Store is not supported. */
@@ -1935,8 +1938,11 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
 
         break;
     }
-    case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_PROCBASED_CTLS2:
-        goto gp_fault;
+    case IA32_FEATURE_CONTROL_MSR:
+    case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
+        if ( !nvmx_msr_write_intercept(msr, msr_content) )
+            goto gp_fault;
+        break;
     default:
         if ( vpmu_do_wrmsr(msr, msr_content) )
             return X86EMUL_OKAY;

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index eca653f2a0f68001353dd1b6c3474f87ae072067..3ca1a267bddaf45d01bfe2b4d860e4f7ca408d0e 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -22,6 +22,7 @@
 
 #include <xen/config.h>
 #include <asm/types.h>
+#include <asm/mtrr.h>
 #include <asm/p2m.h>
 #include <asm/hvm/vmx/vmx.h>
 #include <asm/hvm/vmx/vvmx.h>
@@ -1245,6 +1246,113 @@ int nvmx_handle_vmwrite(struct cpu_user_regs *regs)
     return X86EMUL_OKAY;
 }
 
+/*
+ * Capability reporting
+ */
+int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
+{
+    u64 data = 0, tmp;
+    int r = 1;
+
+    if ( !nestedhvm_enabled(current->domain) )
+        return 0;
+
+    /*
+     * Remove unsupport features from n1 guest capability MSR
+     */
+    switch (msr) {
+    case MSR_IA32_VMX_BASIC:
+        data = VVMCS_REVISION | ((u64)PAGE_SIZE) << 32 | 
+               ((u64)MTRR_TYPE_WRBACK) << 50 | (1ULL << 55);
+        break;
+    case MSR_IA32_VMX_PINBASED_CTLS:
+        /* 1-seetings */
+        data = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
+        data <<= 32;
+       /* 0-settings */
+        data |= 0;
+        break;
+    case MSR_IA32_VMX_PROCBASED_CTLS:
+        /* 1-seetings */
+        data = (CPU_BASED_HLT_EXITING |
+               CPU_BASED_VIRTUAL_INTR_PENDING |
+               CPU_BASED_CR8_LOAD_EXITING |
+               CPU_BASED_CR8_STORE_EXITING |
+               CPU_BASED_INVLPG_EXITING |
+               CPU_BASED_CR3_LOAD_EXITING |
+               CPU_BASED_CR3_STORE_EXITING |
+               CPU_BASED_MONITOR_EXITING |
+               CPU_BASED_MWAIT_EXITING |
+               CPU_BASED_MOV_DR_EXITING |
+               CPU_BASED_ACTIVATE_IO_BITMAP |
+               CPU_BASED_USE_TSC_OFFSETING |
+               CPU_BASED_UNCOND_IO_EXITING |
+               CPU_BASED_RDTSC_EXITING);
+        /* bit 1, 4-6,8,13-16,26 must be 1 (refer G4 of SDM) */
+        tmp = ( (1<<26) | (0xf << 13) | 0x100 | (0x7 << 4) | 0x2);
+        /* 0-settings */
+        data = ((data | tmp) << 32) | (tmp);
+        break;
+    case MSR_IA32_VMX_EXIT_CTLS:
+        /* 1-seetings */
+        /* bit 0-8, 10,11,13,14,16,17 must be 1 (refer G4 of SDM) */
+        tmp = 0x36dff;
+        data = VM_EXIT_ACK_INTR_ON_EXIT;
+#ifdef __x86_64__
+        data |= VM_EXIT_IA32E_MODE;
+#endif
+       /* 0-settings */
+        data = ((data | tmp) << 32) | tmp;
+        break;
+    case MSR_IA32_VMX_ENTRY_CTLS:
+        /* bit 0-8, and 12 must be 1 (refer G5 of SDM) */
+        data = 0x11ff;
+        data |= VM_ENTRY_IA32E_MODE;
+        data = (data << 32) | data;
+        break;
+
+    case IA32_FEATURE_CONTROL_MSR:
+        data = IA32_FEATURE_CONTROL_MSR_LOCK | 
+               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX;
+        break;
+    case MSR_IA32_VMX_VMCS_ENUM:
+        /* The max index of VVMCS encoding is 0x1f. */
+        data = 0x1f << 1;
+        break;
+    case MSR_IA32_VMX_CR0_FIXED0:
+        /* PG, PE bits must be 1 in VMX operation */
+        data = X86_CR0_PE | X86_CR0_PG;
+        break;
+    case MSR_IA32_VMX_CR0_FIXED1:
+        /* allow 0-settings for all bits */
+        data = 0xffffffff;
+        break;
+    case MSR_IA32_VMX_CR4_FIXED0:
+        /* VMXE bit must be 1 in VMX operation */
+        data = X86_CR4_VMXE;
+        break;
+    case MSR_IA32_VMX_CR4_FIXED1:
+        /* allow 0-settings except SMXE */
+        data = 0x267ff & ~X86_CR4_SMXE;
+        break;
+    case MSR_IA32_VMX_MISC:
+        gdprintk(XENLOG_WARNING, "VMX MSR %x not fully supported yet.\n", msr);
+        break;
+    default:
+        r = 0;
+        break;
+    }
+
+    *msr_content = data;
+    return r;
+}
+
+int nvmx_msr_write_intercept(unsigned int msr, u64 msr_content)
+{
+    /* silently ignore for now */
+    return 1;
+}
+
 void nvmx_idtv_handling(void)
 {
     struct vcpu *v = current;

diff --git a/xen/include/asm-x86/hvm/vmx/vvmx.h b/xen/include/asm-x86/hvm/vmx/vvmx.h
index f7423be0bcf4db8b6e27f0679d1727e4c14b61a7..19fe26d68618a4e300bf20b87174b460c626fa1a 100644 (file)
--- a/xen/include/asm-x86/hvm/vmx/vvmx.h
+++ b/xen/include/asm-x86/hvm/vmx/vvmx.h
@@ -163,6 +163,10 @@ int nvmx_handle_vmread(struct cpu_user_regs *regs);
 int nvmx_handle_vmwrite(struct cpu_user_regs *regs);
 int nvmx_handle_vmresume(struct cpu_user_regs *regs);
 int nvmx_handle_vmlaunch(struct cpu_user_regs *regs);
+int nvmx_msr_read_intercept(unsigned int msr,
+                                u64 *msr_content);
+int nvmx_msr_write_intercept(unsigned int msr,
+                                 u64 msr_content);
 
 void nvmx_update_exec_control(struct vcpu *v, u32 value);
 void nvmx_update_secondary_exec_control(struct vcpu *v,